Improvements in computer system designs has led to designs with a high speed microprocessor coupled to multiple memory modules and external components. Current microprocessors operate at a predetermined frequency ranging from 60 mega-hertz to 400 mega-hertz. However, the design of the memory modules and external components coupled to the microprocessor operate on a wide range of frequencies. Typically, the memory modules and external components operate at lower frequency than the microprocessor. To facilitate communication between microprocessors, memory modules, and external components prior art computer systems have developed different busses and bridging schemes. The industry standard architecture ("ISA") and the peripheral component interconnect ("PCI") bus designs are examples of the prior art bussing schemes used to couple microprocessors to memory modules and external components. Using the prior art bussing schemes and bridges, conventional computer systems are able to transfer data asynchronously between memory modules and external components.
FIG. 1 illustrates a prior art data transfer scheme on an asynchronous bus. In particular, system 100 includes component 105 coupled to component 110 via bus 150. Bus 150 is a bidirectional bus used to transfer data between component 105 and component 110. To generate and receive data on bus 150, component 105 includes three logic blocks (115, 120, and 130). Similarly, component 110 includes three logic blocks (140, 160, and 170) that generate and receive data on bus 150.
Component 105 operates at a different frequency than component 110. Accordingly, component 105 also includes metastable synchronizers 131-136. Similarly, component 110 also includes metastable synchronizers 141-146. Using a combination of logic blocks and metastable synchronizers, component 105 and component 110 exchange data. For example, to transfer data from logic block 130 to logic block 160, component 105 initially outputs the data value on line 118 in a first frequency domain. Subsequently, the outputted data is sampled by metastable synchronizers 145 and 146 and transferred to logic block 160. Thus, the metastable synchronizers allow the transfer of data between different frequency domains. Typically, the metastable synchronizers for each component comprise two back-to-back latches designed to have a minimum setup and hold times. The metastable synchronizer design is based on empirical data corresponding to the particular silicon process used to design component 110.
Using metastable synchronizers to transfer data between frequencies, however, creates numerous disadvantages. One disadvantage results from the creation of a race condition. In particular, provided a data block is transferred across a group of metastable synchronizers one of the metastable synchronizers can possibly latch data a cycle later than the remaining metastable synchronizers, thus resulting in the receiving component incurring data corruption. To counteract race conditions some prior art computer system require timing constraints on the input/output of all components within the computer system. Following a set of timing constraints, however, reduces the throughput of data across system 100.
Another disadvantage of using metastable synchronizers to transfer data between frequencies results from the incurred costs. For example, provided a thirty-two bit bus is coupled to a component, thirty-two metastable synchronizer are required. Thus, the circuitry included in the component increases, resulting in a higher cost during the manufacturing of the component. Furthermore, the increase in circuitry results in a larger die size, thus reducing manufacturing yield.